Multi-processor Model
202309061217
Status: #idea
Tags: OS
Multi-processor Model
Multi-core vs Multi-processing
Multi-core
- L2/L3 cache is shared between cores
- Can have upto ~100 cores
Multi-processor
- RAM sharing
- Can be via motherboard, or via network (in the case of distributed computing)
- Can scale to even 1000x processors
- 2 types
- Asymmetric
- Each processor is assigned a specific task
- Example: A co-processor
- Symmetric
- Local registers and cache are separate, but share main memory
- Can even be at ISA level like big.LITTLE (P-cores & E-cores)
- Asymmetric
Multi-processor Memory Model
Uniform Memory Access (UMA)
- Physically impossible
- All levels of memory have equal access time
Non-Uniform Memory Access (NUMA)
- Getting data from different levels of memory takes different amount of time
- Accessing my own L1 is faster than another core's L1
NO Remote Memory Access (NORMA)
- Can not access another core's data directly
Procrastination
- Putting a job off, to increase shutdown time and save power
- Example
J1: 0->10 (1 EU)
J2: 10->30 (2 EU) - Execute J1 from 0->1. Shutdown till 28. Execute J2 from 28->30
Info
Bitmap operations are usually to the order of the size of the bitmap
Warning
We count loops down instead of up, because checking for 0 requires a single gate.