Multi-user Operating System
202309061106
Status: #idea
Tags: OS
Multi-user Operating System
- Each user gets a budget
Computer Architectures
Single cycle design
- No overlap
- Von-Neumann architecture can be used
- All instructions are designed for the maximum time, it can take
Multi-cycle design
- Wait till each instruction is over
- Each task is broken into stages
Pipelined design
- Has ILP (Instruction Level Parallelism)
Modern day Intel processors use a superscalar architecture
Internally, CISC gets split into RISC-like instructions and those are pipelined
Pipelining is not possible in Von Neumann (Princeton) model, due to simultaneous need for instruction cache and data cache
Modified Harvard model allows us to modify instructions on the fly.
Figure below shows the path taken
graph TB subgraph L1 direction LR 0[L1 Data] 1[L1 Instruction] end L2 L2 -->|1| 0 -->|2| L2 -->|3| 1
Locality of Reference
A program works w.r.t. locality of reference
- Temporal locality: If I access
aat, then it is likely to be accessed at - Spatial locality: If I access
a[0], it is likely that I accessa[1]also
Example
for (i: 0 -> 1024) {
for (j: 0 -> 1024) {
A[i][j] = 0; // Locality of reference is maintained
A[j][i] = 0; // Inefficient. Locality lost
}
}
goto kills locality of reference
Intel Core i3 - Hyperthreading (2 hardware threads can run in parallel on a single processor)
Intel Core i5 - Turbo boost
Intel Core i7 - Hyperthreading + Turbo boost
Intel Core i9 - Hyperthreading + 2 Turbo boost frequencies
Intel usually processes 20 instructions in parallel, with 4 simultaneous pipelines and 2 simultaneous hardware threads.
Intel has
In-order entry
Loop unrolling vectorises the operation
ARM processors often have dynamic voltage-frequency scaling, i.e. the CPU moves on its own voltage-frequency curve